1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device suitably applicable to an integrated circuit for driving a thin-model display device such as a liquid crystal panel or a plasma display panel.
A gate driver and a source or data driver are known as integrated circuits for driving a liquid crystal display panel in which liquid crystal and a TFT (Thin Film Transistor) are combined. The gate driver functions to selectively drive gate lines running horizontally on the display panel in an order from the top. The data driver converts a picture data signal to a voltage to be applied to liquid crystal and applies the voltage to a pixel electrode connected to a selected gate line.
The data driver has a limited number of outputs mountable on a single integrated circuit. For that reason, a plurality of integrated circuit drivers are used to realize the desired resolution of the liquid crystal display panel. For instance, eight integrated circuit drivers are needed to realize the XGA (eXtended Graphics Array) liquid crystal panel consisting of 1024×768 dots, each of the drivers having 384 outputs (128×3 in RGB), and ten drivers are needed to realize the SXGA (Super eXtended Graphics Array) consisting of 1280×1024 dots.
2. Description of the Related Art
FIG. 5 illustrates an arrangement of the conventional data driver. In the arrangement, four individual integrated circuit drivers 102 are used for single liquid crystal display panel 101. The input of each of the drivers 102 is connected to a plurality of common data lines DATA and a common clock line CLK, via which a data line and a clock signal are supplied to the integrated circuit drivers 102 in parallel. The output of each of the integrated circuit drivers 102 are connected to source lines of the liquid crystal display panel 101.
Each of the integrated circuit drivers 102 is equipped with a gate circuit in the input port via which the data signal is taken. The gate circuit analyzes the data signal applied to all the drivers 102. Then, the gate circuit opens its own gate and latches the data signal if the data signal should be taken in. After the gate latches the data signal, the gate circuit closes the gate. Thus, each of the drivers 102 is disabled while the other drivers latch the data signal. Thus, it is possible to reduce power consumed in the data driver.
The interconnections from the common data lines DATA to the respective drivers 102 have crossing points in the parallel style in which the data signal is sent in parallel. A printed-circuit board on which the drivers 102 are mounted employs through holes used to connect the data lines DATA and input lines extending to the drivers 102 formed in another layer. The above interconnection is achieved using a multilayer board having four to six layers.
Since the data lines DATA and the clock line CLK are used to drive all the drivers 102, a drive circuit connected to these lines is needed to have a high drivability. However, considerable EMI arises from the highly driven lines.
FIG. 6 shows another arrangement of the conventional data driver. The arrangement shown in FIG. 6 is the same as that shown in FIG. 5 in that the outputs of the integrated circuit drivers 103 are connected to the source lines of the liquid crystal display panel 101, but is different therefrom in that the data lines DATA and the clock line CLK are arranged so as to cascade the drivers 103.
The data signal and the clock signal that travels on the data lines DATA and the clock line CLK are sent to the drivers 103 in turn. The cascaded arrangement does not have crossing points of the data lines DATA that exist in the parallel formation. Thus, the printed-circuit board on which the driver 103 is mounted may be formed by a reduced number of layers, for example, two layers. This reduces the cost of the printed-circuit board. Further, the circuit that supplies the data signal and the clock signal to the data lines DATA and the clock line CLK is required to drive only the first driver 103, and may have a reduced drivability. This contributes to reduction in EMI resulting from the data lines DATA and the clock line CLK.
However, it should be noted that the data cascading system differs from the parallel formation in that the data signal passes inside the integrated circuit of the driver and is sent to the next stage. Therefore, the driver is required to continue to input the data signal for the next stage even after the data signal that is to be taken in its own integrated circuit is completely latched.